The present invention relates to a memory device, and particularly to a method for precharging the input/output lines of the memory device.
There are various signal transmitting lines in semiconductor memory devices which are following the trend of increasing integration and speed. For example, input/output lines for transmitting input/output data serve as paths for producing, through an output buffer, data read out from a selected memory cell, and commonly serves as paths for supplying external data to a selected memory cell. In the memory devices which are currently used, since information is transmitted through a pair of bits, the input/output lines for transmitting data also are made of a pair of lines corresponding to the pair of bits. In the pair of input/output lines, one of the lines represents memory cell information, while the other line represents a complement value thereof. When information of the selected memory cell appears on such input/output lines in the form of voltages, a sense amplifier senses and amplifies the difference between the two voltages, thereby making it possible to validly recognize the information. In order to efficiently carry out the signal transmission mentioned above, the transmission speeds have to be fast not only in the bit lines of the memory array, but also in the input/output lines thereof, and it has to be taken into account how speedily the voltage potentials input/output lines are split.
FIG. 1 illustrates a column circuit of a memory device, showing the process of transmitting information through bit lines, a sense-amplifier and input/output lines, after reading out the information from a memory cell of a memory device. As shown in this drawing, a p-type sensing amplifier 20 and an n-type sensing amplifier 40 are connected between a bit line BL and a complementary bit line BL which are connected to a memory cell array 10, while a separate gate 30 is connected between the p-type sensing amplifier 20 and the n-type sensing amplifier 40, the separate gate 30 connecting respectively the bit line BL and the complementary bit line BL to the memory cell array 10.
The separate gate 30 is controlled according to separating clock pulses .phi.ISO, while the bit lines BL, BL are connected through a column gate 50 to input/output lines IO, IO, while the column gate 50 is controlled according to column selecting signal CSL output from a column decoder which is not shown. Between the input/output line IO and the complementary input/output line IO, there are connected in parallel a first input/output line precharging circuit 18 and a second input/output line precharging circuit 19. The first circuit 18 includes NMOS transistors 13 and 14 which receive a first precharging signal .phi.IOPR through their gates, while the second circuit 19 includes three NMOS transistors 15, 16 and 17 which receive a second precharging signal .phi.IOP through their gates. A connection to the channels of the two transistors 13 and 14 in the first precharging circuit 18 is supplied with input/output line precharging voltage VIOPR of (1/2)Vcc level.
In the second precharging circuit 19, the channels of the NMOS transistors 15 and 17 are respectively connected between a power terminal Vcc, and the input/output lines IO and IO, while the channel of the NMOS transistor 16 is connected between the input/output lines IO, and IO. Meanwhile and an input/output sense amplifier which is not shown, capable of sensing and amplifying the potential difference between the input/output lines, is connected to the input/output lines IO, IO. It is noted that such structure is known. It is further noted that the column circuit of FIG. 1 is a basic circuit for describing the precharging methods of the present invention.
FIGS. 2A and 2B illustrate the conventional embodiments for generating the first and second precharging signals .phi.IOPR, .phi.IOP. Referring to FIG. 2A, the first precharging signal .phi.IOPR is obtained by inverting a row address signal RAi. Referring to FIG. 2B, the pulse width of a column address transition signal ATS is adjusted by three inverters 22, 23 and 24 and a NOR gate 25, and the signal output from the NOR gate 25 together with a column enabling signal .phi.YE are applied to a NAND gate 26. The signal output from the NAND gate 26 is applied to an inverter 27 to generate the second precharging signal .phi.IOP. It is apparent from FIGS. 2A and 2B that conventionally the first precharging signal .phi.IOPR is generated according to the row address signal RAi. It is further apparent that the second precharging signal .phi.IOP is enabled to high state only when the column address is transmitted in the condition of the column enabling signal .phi.YE being enabled to high state, so as drive the second precharging circuit 19 of FIG. 1.
Now the operation of the column circuit of FIG. 1 which is related to the conventional input/output precharging method will be described referring to the operational timing diagrams of FIG. 2C. First, since the first precharging signal .phi.IOPR is high state before a row address strobe signal RAS is enabled to high state, the input/output line precharging voltage VIOPR is supplied through the first precharging circuit 18 to the lines IO, IO, so that the input/output lines are precharged and equalized to (1/2)Vcc level. Thereafter, if the signal RAS is enabled to low state, and if the row address signal RAi is applied, the signal .phi.IOPR is disabled to low state. When the information of the memory cell, which is selected by input of the row address signal RAi, appears on the bit lines, the sensing clock pulses LA, LA are enabled so that the potential difference between the lines BL, BL is amplified as much as .DELTA.VO. In this case, it is a well known fact that the bit lines BL, BL are equalized to (1/2)Vcc level.
When the bit lines are split as much as a potential difference of .DELTA.V0 by the sensing amplifiers 20 and 40, the column enable signal .phi.YE is enabled to high state, so that the column selecting signal CSL is enabled to high state. Thus, the bit lines BL, BL, which are split by as much as a given potential difference, are connected to the input/output lines IO and IO which are precharged to a (1/2)Vcc level by means of the first precharging signal .phi.IOPR. A charge sharing occurs between the input/output lines and the bit lines which are connected by the column gate 50.
As the result of the charge sharing, the potential of the bit line which is higher than the potential of the precharge level (1/2)Vcc, is dropped as much as .DELTA.V1, while the potential of the bit line which is lower than the potential of the precharged level (1/2)Vcc, is increased as much as .DELTA.V2, as shown in FIG. 2C. Accordingly, immediately after the connection between the pair of the bit lines BL, BL and the pair of the input/output lines IO, IO, the potential difference between the bit lines is reduced to .DELTA.V0-(.DELTA.V1+.DELTA.V2)=.DELTA.V3. Then the potentials of the bit lines BL and BL are respectively charged to Vcc and 0 voltage by the p-type sensing amplifier 20 and the n-type sensing amplifier 40. Meanwhile, the input/output lines IO and IO are also split in accordance with the level variation of the bit lines. In this case, however, since the potential difference .DELTA.V3 which appears initially on the input/output lines is low, it takes much time to form a desired potential difference, with the result being that the overall read-cycle of data is extended. That is, when the potential difference between the bit lines is transferred through the column gate 50 to the input/output lines, any undesired potential difference should be limited to the minimum.
In the process of such operation, the second precharging signal .phi.IOP controlling the second precharging circuit 19 is enabled only when there is a transition in the column address, that is, when the column address transition signal ATS is triggered from high state to low state, as described above. Therefore, as described above, when the data are accessed in accordance with the row address strobe signal RAS without transition of the column address (T.sub.RAC condition), the second precharging signal is maintained at low state. That is, the second precharging circuit 19 of FIG. 1 is not driven, with the result that the splitting speed of the input/output lines is delayed in an RAS active cycle, and that a precharge voltage terminal (1/2)Vcc becomes unstable during the precharging of the input/output lines.
Furthermore, according to the conventional method, if the RAS signal is enabled to high state, the input of the row address signal RAi is terminated, that is, the row address signal RAi is enabled to low state, and consequently, the first precharging signal .phi.IOPR is enabled to high state, with the result that the input/output lines IO, IO are precharged to (1/2)Vcc level. Under this condition, however, if the input/output line precharging voltage terminal VIOPR of half-Vcc level and the input/output lines IO and IO are connected, current from the input/output line IO (or the input/output line IO) having a potential higher than (1/2)Vcc level flows into the precharge voltage terminal VIOPR, and then, the current from the precharge voltage terminal VIOPR flows into the complementary input/output line IO (or the input/output line IO) having a potential lower than the precharge level. Consequently, there arises the problem that the characteristic level of the input/output line precharging voltage VIOPR, i.e., the (1/2)Vcc value, becomes unstable.